In a significant advance for next-generation computing, a research team has successfully engineered and fabricated the world’s first fully functional chip that combines two-dimensional (2D) materials with conventional silicon circuitry. This breakthrough overcomes a persistent and critical challenge in electronics: how to merge the remarkable properties of atomically thin 2D materials with the mature, globally adopted silicon-based chip manufacturing ecosystem. The resulting hybrid chip architecture promises to smash through the performance bottlenecks that currently limit data-intensive applications like artificial intelligence.
The new device, developed by scientists at Fudan University, integrates an ultrafast 2D flash memory component with a standard complementary metal-oxide-semiconductor (CMOS) silicon base. This achievement provides a viable pathway for translating the extraordinary potential of 2D materials, which have largely been confined to laboratory research, into practical, high-performance systems. By creating a chip that supports high-speed parallel operations with an impressively high manufacturing yield, the researchers have laid the groundwork for a new era in information technology, particularly for memory and data storage systems that can keep pace with the voracious demands of AI.
A Fundamental Integration Hurdle
For years, the promise of 2D materials—substances just one or a few atoms thick—has tantalized the semiconductor industry. Their unique electronic properties offer capabilities far beyond those of silicon, which is reaching its physical limits. However, integrating these fragile, ultra-thin materials directly onto a silicon chip has been a major engineering roadblock. A standard CMOS circuit is not a smooth, flat surface; it is a complex, rough landscape of pre-existing components and connections. Directly fabricating a material that is only one to three atoms thick onto such a surface is fraught with peril, as the delicate 2D layer can easily break, compromising its performance and rendering the device useless.
This physical incompatibility has been the core challenge preventing the development of hybrid 2D-silicon systems. While researchers have made progress in demonstrating the potential of individual 2D components, creating a complete, functional system that could be manufactured at scale remained elusive. The Fudan team recognized that a new method was needed to bridge the gap between these two vastly different material platforms without destroying the advantages of each.
A Modular and Monolithic Solution
The team’s solution was an innovative modular integration strategy. Instead of attempting to grow or place the 2D material directly onto the finished silicon wafer, they fabricated the 2D memory circuits and the CMOS logic circuits separately in parallel. This allowed each component to be produced in its optimal environment without compromise. The true innovation came in how they combined these disparate modules into a single, cohesive chip.
To achieve this, they employed a high-density monolithic interconnection technology. This process uses microscopic through-holes to create vertical connections between the two layers, effectively stacking and wiring the 2D material circuit on top of the silicon CMOS circuit. This technique allows the 2D materials to be tightly coupled with the CMOS substrate at an atomic scale, ensuring robust communication between the layers without the risk of physical damage. The researchers have named their architecture the “Changying (CY-01) architecture,” and the underlying methodology the Atom-to-Chip (ATOM2CHIP) technology.
Breakthrough Speed with “PoX” Memory
At the heart of the new chip is an ultrafast 2D flash memory device the team has dubbed “PoX.” This component is the key to the chip’s enhanced performance. In research published earlier in 2025 in the journal Nature, the team first introduced the PoX prototype, which demonstrated a program speed of just 400 picoseconds. This made it the fastest semiconductor charge storage technology ever recorded, providing a physical basis for shattering existing speed limits in data storage and retrieval.
The new hybrid chip represents the first successful engineering of this PoX technology into a complete, system-level application. While the prototype proved the device’s potential, integrating it with the control logic of a CMOS circuit was the necessary next step to create a usable product. By achieving this, the team has created a 2D NOR flash memory chip that leverages the unprecedented speed of the PoX device for practical computing tasks.
Chip Performance and Production Viability
The resulting 2D-silicon hybrid flash chip exhibits impressive specifications that validate its design. It successfully supports 8-bit instruction operations, 32-bit high-speed parallel operations, and random access capabilities, all of which are essential for modern computing. Its overall operation speed significantly surpasses that of existing flash memory technologies, addressing a key bottleneck in AI systems where the speed of data access often limits computational power.
Perhaps most importantly for its future prospects, the team’s fabrication process has proven to be remarkably reliable. They have achieved a memory cell yield rate exceeding 94 percent, with one report citing a specific figure of 94.3 percent. This high yield is a critical milestone, demonstrating that the modular integration approach is not just a laboratory curiosity but a robust and scalable method suitable for industrial manufacturing. The chip has already completed the tape-out process, a final step in the design phase before it is sent for mass production.
Paving the Way for Future Electronics
This achievement is expected to have wide-ranging implications for the future of information technology. It provides a tangible model for accelerating the transition of other next-generation disruptive technologies from research to application. Scientists believe that memory devices are likely to be the first type of 2D electronic component to be commercialized. This is because their performance metrics dramatically outperform current technologies, and they have slightly less stringent requirements for material quality and manufacturing processes compared to logic circuits like CPUs.
The Fudan team, co-led by researchers Zhou Peng and Liu Chunsen, reached this point after a dedicated five-year period of exploration and development. Their systematic approach was highlighted by a 2024 publication in Nature Electronics, which detailed their success in achieving a high yield rate of 2D materials on an ideal substrate. That earlier work laid the essential foundation for tackling the more complex and demanding task of integrating these materials with a real-world, topographically challenging CMOS substrate. By solving this puzzle, they have opened the door for a new class of powerful and efficient electronic devices built on a hybrid 2D-silicon platform.
